Siemens Calibre Platform Extends Early Design Verification Solution | 黑森尔电子
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Siemens Calibre Platform Extends Early Design Verification Solution

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发布日期: 2022-07-30, Sierra Wireless

Siemens Digital Industries Software has expanded its integrated circuit (IC) physical verification platform, Calibre, with a range of electronic design automation (EDA) early-stage design verification capabilities that “shift left” the physical and circuit verification tasks to the higher end of the design and verification process. Identify, analyze, and resolve complex IC and system-on-a-chip (SoC) physical verification problems at an early stage, helping IC design teams and companies accelerate tape-out.

Identifying and solving problems earlier in the design cycle not only helps to compress the overall verification cycle, but also creates more time and opportunity to improve the quality of the final design. Siemens uses certified signoff standards to provide adjusted inspection support for early-stage analysis, validation and optimization strategies, helping design firms streamline the design process, increase designer efficiency, and reduce time-to-market.

Michael Buehler-Garcia, Vice President, Product Management, EDA Calibre Design Solutions, Siemens, said: "Continuing our technology leadership in EDA requires a deep understanding of the specific challenges our customers face in their day-to-day work, and those challenges that drive continuous improvement. "By adding early design verification capabilities to Calibre, our customers can take advantage of new technologies and bring high-quality silicon products to market quickly, no matter what stage of design they are in."

New features of the Calibre platform include:

• Calibre RealTime Custom and Calibre RealTime Digital software tools. These tools provide in-line, signoff-quality Calibre DRC for custom, analog/mixed-signal, and digital designs. The Calibre RealTime interface directly invokes the Calibre analysis engine, runs the foundry-certified sign-off Calibre rule set, and provides instant feedback and compliance recommendations for design violations, helping to speed designs and improve the quality of results. Calibre RealTime Digital now enables in-line fill with the Calibre Yield Enhancer SmartFill feature, allowing designers to obtain foundry signoff quality fill directly from within the design platform, and Calibre RealTime Custom adds the ability to automatically track DRCs across multiple zones, Ability to fix, track, and review multiple edits at the same time.

• The Calibre nmDRC-Recon model in Calibre RealTime Digital enables intelligent, automated analysis of premature and incomplete designs across blocks, macroblocks, and full-chip layouts, discovering and fixing bugs early in the design and verification process Significant impact on physical layout. In addition to the speed advantages and debug advantages already available to the Calibre nmDRC-Recon model, Siemens has now added the ability to flexibly "gray-box" immature units and modules, while still maintaining a high level of sensitivity to connections. DRC checks are performed on interfaces of adjacent modules or higher-layer metals. The "gray box" feature avoids irrelevant DRCs, further improving execution speed and designer debugging efficiency, delivering up to 50% faster run times compared to nmDRC-Recon alone.

• Calibre nmLVS-Recon software enables intelligent, automated circuit verification analysis for immature and incomplete designs. With Calibre nmLVS-Recon software, designers can efficiently perform Short Isolation to find circuit errors. Short Extraction Mode in Calibre nmLVS-Recon requires no changes to design entry or foundry rulesets, and performs only the short extraction step of Calibre nmLVS, which can perform LVS up to 30 times faster, allowing designers to Complete multiple iterations of verification

The Calibre nmPlatform tool suite is unique in the EDA industry, integrating all major IC design and layout implementation tools. This seamless integration allows design teams to easily run Calibre tools at the intellectual property block (IP), functional block/macroblock, full-chip level from within their custom design or place-and-route (P&R) design environment. In addition, the Calibre platform offers unique viewing and debugging capabilities that speed up all design stages.

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