To operate at optimal power and higher speeds with a smaller physical size than competing products from other vendors.
In addition, Lattice has integrated more and faster connectivity solutions and enhanced security standards into the Nexus 2 platform. In terms of connectivity, the Nexus 2 supports multi-protocol 16G SERDES through the integrated PCIe Gen 4 controller, with MIPI D and C-PHY speeds of up to 7.98 Gbps. The platform also supports the use of high-speed LPDDR4 storage for faster overall system performance.
Regarding security, the Nexus 2 supports the 256-bit AES-GCM and SHA3-512 standards and is FIPS 140-3 Level 2 compliant, ensuring that devices utilizing this chip can have enhanced security in sensitive and mission-critical environments. Additionally, because such FPGAs are typically used in longer-lived devices, the Nexus 2 platform is ready for the post-quantum era, greatly easing the pressure on system designers who know that these devices will be able to cope with even the potential security challenges of the future.
The first device in the Nexus 2 platform is the Lattice Certus™-N2 family of general-purpose FPGAs, and many of Lattice's customers have already received samples. In addition, Lattice has upgraded its Lattice Propel and Lattice Radiant design software tools to support these new chips, making it easier for system designers to customize them to their specific needs.
With these new features, the Certus-N2 chip will be able to deliver higher performance in existing applications, opening up a range of opportunities for new applications. For example, in real-world applications, power consumption is up to three times lower than comparable products, meaning the new device consumes less power, operates more reliably, and runs longer in battery-powered environments.
The performance improvements of the new platform are realized in several ways. First, faster bandwidth connectivity between SERDES, DRAM, flash, and PCI allows the system to work more efficiently and connect with higher data rate peripherals. This is a key reason why Nexus 2 FPGAs boot up so much faster (up to 20x) than some competitors.
Because FPGAs typically act as intermediaries between sensors and computing and provide points of interconnection in larger systems, these new capabilities create opportunities for new applications. For example, in modern automotive designs with partitioned architectures, fast, reliable interconnections are needed between these partitions. Additionally, the Certus-N2 wakes up almost instantly when the car is in motion and can play a significant role in responding to externally triggered data. Similar applications become possible in environments where high-speed motor-controlled robots are used, such as in manufacturing.
Other key architectural benefits of the Nexus 2 include twice as many customizable logic cells and more than three times as many DSP cores as the first-generation Nexus device, up to 520. Together, these features can run more advanced algorithms, offering the potential to improve the accuracy and speed of edge inference applications such as human or object presence detection, image or audio recognition, and more.
While these applications may not receive as much attention as today's latest GPUs, the mission-critical nature of the tasks handled by small FPGAs makes them an absolutely essential part of many of today's devices. Controlling startup processes, connecting sensors to computing centers, running time-sensitive specialized algorithms, and many more functions that small FPGAs are capable of, are all central to the operation of advanced systems.
As today's advanced devices continue to utilize all types of advanced features, the demands on the chips that support these essential operations continue to grow. As a result, enhancing the performance of the Nexus family of small FPGAs is an important and far-reaching step toward powering the next generation of advanced systems.
