On June 27, South Korean media Business Korea reported on June 24 that Samsung Electronics' semiconductor packaging industry has made significant progress and will lead TSMC in the field of panel-level packaging (PLP).
Kyung Kye-hyun, former head of Samsung Electronics' semiconductor (DS) department, attended the shareholders' meeting in March this year and elaborated on the need to promote PLP technology.
He explained: "AI semiconductor chips (rectangular components with circuits) are usually 600mm x 600mm or 800mm x 800mm in size, so technologies such as PLP are needed, and Samsung is currently actively developing and strengthening cooperation with customers."
TSMC is studying a new advanced chip packaging method that uses rectangular substrates instead of traditional circular wafers, thereby placing more chips on each wafer.
Sources revealed that the rectangular substrate is currently being tested and measures 510 mm x 515 mm, with a usable area more than three times that of a circular wafer. The use of a rectangle means that there will be less unused area left on the edge.
Nikkei Asia reported: "TSMC's research is still in the early stages and mass production is expected to take several years. Although TSMC was previously skeptical about using rectangular printed circuit boards, its entry into research represents an important technological shift."
Market research firm IDC reported that Nvidia needs half of TSMC's CoWoS capacity to fulfill its AI semiconductor orders, but only about one-third of it can actually be implemented. TSMC plans to more than double the capacity of the process by the end of the year, however, competition from fabless companies such as AMD and Broadcom for TSMC's CoWoS output makes this goal challenging.
