Agile Analog has introduced its first series of analog subsystems, covering power management, PVT detection, and sleep management. These innovative digital packaging subsystems allow multiple analog ips to be placed directly into the digital design process and connected via a standard peripheral bus such as AMBA APB, significantly reducing the amount of work required to integrate multiple analog ips into any ASIC. These subsystems look like an ordinary digital IP block, with the standard interfaces that engineers expect to make it easy to understand and work with. As a result, time to market, cost and risk are greatly reduced. Initially, the company is rolling out three subsystems: agilePMU for power management, agilePVT-PVT sensor and agileSMU for sleep management.
The IP modules in the subsystem are all derived from Agile Analog's existing portfolio of customizable analog IP products. This allows each module in the subsystem to be customized to the exact requirements of the customer while sitting in the entire digital wrapper. As with all Agile Analog IP, the digital packaging subsystem is process and foundry independent, and each design is optimized for a customer's specific PDK. Integrating IP into subsystems further enhances customer designs by eliminating duplicate simulation functions, reducing design rule checking (DRC) requirements, and optimizing interconnections. These can improve noise resistance, reduce power consumption and reduce area.
Agile Analog's subsystems provide a complete set of supporting materials, including the System Verilog model, that can be easily integrated into a customer's existing digital verification process. "I'm excited to announce our first three subsystems," said Chris Morrison, Director of Product Marketing at Agile Analog. Customers are always looking for ways to shorten time to market, reduce costs and reduce risk, and our new digital packaging subsystem does just that. Crucially, customers no longer have to deal with the complex mixed-signal boundary between analog and digital, greatly reducing their design effort and reducing the risks typically associated with integrating complex analog IP arrays.
Another key benefit for the customer is that all verification requirements from analog to digital, mixed signals, and boundaries are performed by Agile simulation. This significantly reduces customer design and validation time, reduces risk in the design process, reduces licensing costs for mixed-signal design tools, and simplifies integration. Customers can now add analog capabilities to provide product differentiation without the need for professional analog and mixed-signal engineers and associated expensive tool chains.
AgileSMU sleep management subsystem
AgilePMU subsystem is an efficient and highly integrated power management for SoC/ASIC. With power-on reset, multiple low voltage differential regulators and associated reference generators. The agilePMU subsystem is designed to ensure low power consumption while providing optimal power management capabilities. The agilePMU subsystem is equipped with an integrated digital controller that provides precise control over startup and shutdown, supports power sequencing, and allows a separate programmable output voltage for each LDO. The status monitor provides real-time feedback on the current state of the subsystem, ensuring optimal system performance.
AgilePVT sensor subsystem
Monitoring process, voltage and temperature changes is critical to optimizing the power and performance of modern SoCs/Asics, especially for advanced node and FinFET processes. The agilePVT sensor subsystem is a low-power integrated macro consisting of process, voltage, and temperature sensors and associated reference generators for on-chip monitoring of the physical, environmental, and electrical characteristics of devices. The agilePVT subsystem is equipped with an integrated digital controller for precise startup and shutdown control. The status monitor provides real-time feedback on the current state of the subsystem, ensuring optimal system performance throughout the product lifecycle.
AgileSMU sleep management subsystem
The agileSMU subsystem is a low-power integrated macro consisting of the basic IP modules needed to safely manage waking up the SoC from sleep mode. Typically included is a programmable oscillator for low-frequency SoC operations and RTCS, multiple low-power comparators that can be used to start wake sequences, and a power-on reset that provides a robust start reset for the SoC. The agileSMU subsystem is equipped with an integrated digital controller for precise control of wake up commands and sequencing. The status monitor provides real-time feedback on the current state of the subsystem, ensuring optimal system performance throughout the product lifecycle.
Agile Analog is changing the world of analog IP with its innovative, configurable, multi-process analog ™ IP technology Composa™. Headquartered in Cambridge, UK, and with a growing number of partners and customers worldwide, Agile Analog has developed a unique approach to automatically generating Analog IP to meet customers' exact specifications on almost any process at any foundry. The company offers a wide and expanding selection of analog IP and subsystems for power management, data conversion, IC health and monitoring, security, and already-online domains. Agile Analog's new approach leverages the time-tested analog circuits in its Composa library to create customized and proven analog IP solutions. This shortens time to market, improves quality and helps accelerate innovation in semiconductor design.
