Microchip Technology now makes 5G performance possible with the first single-chip, highly integrated, low-power, multi-channel IC and the company's IEEE 1588 PTP and clock recovery algorithm software modules.
Rami Kanama, vice president, Microchip timing and Communications Business Unit said："Our latest ZL3073x/ 63X / 64X network synchronization platform implements sophisticated measurement, calibration and adjustment functions that significantly reduce time errors in network equipment to meet the most stringent 5G requirements," "A unique flexible architecture for achieving the necessary channel density as well as high-performance, low-jitter synthesizers helps simplify the design of timing cards, line cards, radio units (RU), centralized units (CUs) and distributed units (DUs) for 5G wireless access networks (RAN)."
The company's measures, calibration and the ability to tune to ensure that the 5 G system to provide the ITU - T standard g. 8273.2 class C (30 ns Max | | TE) and emerging class D (5 ns Max | Tel |) time error requirement. The architecture offers flexibility, providing up to five separate DPLL channels while consuming only 0.9W of power in a compact 9mm x 9mm package, while reducing board space, power supply and system complexity.
Using five ultra-low jitter synthesizers, the latest platform provides the 100FS RMS jitter performance required for high-speed interfaces in the latest 5G Ru, Du and Cu systems.
The company's network synchronization platform software integrates the ZLS30730 high-performance algorithm and the ZLS30390 IEEE 1588-2008 protocol engine. Both are widely used on 3G, 4G and 5G networks with precise timing capabilities.
This network synchronization platform integrates seamlessly with the company's line of precision 5G oscillators. Its broad portfolio of timing and clocking solutions, including clock generation, fanout buffers and jitter attenuation solutions, as well as quartz and MEMS oscillators, is complemented by an extensive family of Ethernet PHY devices.
